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| preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com \ cdb5521/22/23/24/28 cdb5521/22/23/24/28 evaluation board and software features l evaluation board and software supports all chips: cs5521, cs5522, CS5523, cs5524, and cs5528 l direct thermocouple interface l rs-232 to pc with test modes l on-board 80c51 microcontroller l on-board voltage reference l lab windows/cvi tm evaluation software C register setup & chip control C data capture C fft analysis C time domain analysis C noise histogram analysis l on-board charge pump drive circuitry general description the cdb5521/22/23/24/28 is an inexpensive tool de- signed to evaluate the performance of the cs5521, cs5522, CS5523, cs5524, and cs5528 analog-to-dig- ital converters (adc). the evaluation board includes a 2.5 v voltage reference, an 80c51 microcontroller, an rs232 driver/receiver, and firmware. the 8051 controls the serial communication between the evaluation board and the pc via the firm- ware, thus, enabling quick and easy access to all of the cs5521/22/23/24/28s registers. the cdb5521/22/23/24/28 also includes one installed adc sample, and software for data capture, time do- main analysis, histogram analysis, and frequency domain analysis. ordering information cdb5521/22/23/24/28 evaluation board ain1+ ain1- ain2+ ain2- ain3+ ain3- ain4+ ain4- nbv cpd nbv drive circuitry crystal 32.768 khz ref+ ref- voltage reference j2 +5 analog -5 analog agnd cs5522 CS5523 cs5524 cs5528 +5 digital dgnd leds a1 a0 sclk sdo sdi cs 80c51 microcontroller test switches crystal 11.0592 mhz reset circuitry rs232 driver/receiver rs232 connector j1 3 2 1 on off cs5521 may 00 ds317db2
cdb5521/22/23/24/28 2 ds317db2 table of contents 1. part i: hardware .......................................................................................................... ..... 4 1.1 introduction .............................................................................................................. .......... 4 1.3 using the evaluation board ............................................................................................... 8 1.4. power connections ........................................................................................................ ... 8 1.5 negative bias voltage ..................................................................................................... ... 8 1.6 software .................................................................................................................. ........... 9 1.7. writing your own interface software ................................................................................ 9 2. part ii: software ......................................................................................................... .... 13 2.1 installation procedure .................................................................................................... .. 13 2.3 menu bars overview ........................................................................................................ 14 2.4 setup window overview .................................................................................................. 15 2.5 data fifo window overview .......................................................................................... 15 2.6 histogram window overview ........................................................................................... 16 2.7 frequency domain window (i.e. fft) ............................................................................. 17 2.8 time domain window overview ...................................................................................... 18 2.9 calibration window overview .......................................................................................... 19 2.10 trouble shooting the evaluation board ......................................................................... 19 list of figures figure 1. cs5522 analog section ................................................................................................ ... 5 figure 2. cs5524/28 analog section ............................................................................................. .6 figure 3. digital section ...................................................................................................... ............ 7 figure 4. power supplies ....................................................................................................... ......... 8 figure 5. main menu ............................................................................................................ ......... 21 figure 6. setup window ......................................................................................................... ....... 21 figure 7. data fifo window..................................................................................................... .... 22 figure 8. frequency domain analysis .......................................................................................... 22 figure 9. calibration menu ..................................................................................................... ....... 23 figure 10. time domain analysis ................................................................................................ .23 figure 11. histogram analysis (using the cs5524 with default register settings and 24-bit output words) ...................................................................................................... 24 figure 12. cdb5521/22/23/24/28 component side silkscreen .................................................... 25 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ ibm, at and ps/2 are trademarks of international business machines corporation. windows is a trademark of microsoft corporation. lab windows and cvi are trademarks of national instruments. spi tm is a trademark of motorola. microwire tm is a trademark of national semiconductor. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com. cdb5521/22/23/24/28 ds317db2 3 figure 13. cdb5521/22/23/24/28 component side (top) ............................................................. 26 figure 14. cdb5521/22/23/24/28 solder side (bottom) ............................................................... 27 list of tables table 1. header descriptions................................................................................................... ....... 9 table 2. microcontroller read/write commands via rs-232 ....................................................... 10 table 3. microcontroller conversion commands via rs-232 ....................................................... 10 table 4. microcontroller self calibration commands via rs-232 ................................................. 11 table 5. microcontroller system calibration commands via rs-232 ........................................... 12 cdb5521/22/23/24/28 4 ds317db2 1. part i: hardware 1.1 introduction the cdb5521/22/23/24/28 evaluation board pro- vides a means of testing the cs5521/22/23/24/28 analog-to-digital converters (adcs). the board interfaces the converters to an ibm tm compatible pc via an rs-232 interface while operating from a +5 v and -5 v power supply. to accomplish this, the board comes equipped with an 80c51 micro- controller and a 9-pin rs-232 cable, which physi- cally interfaces the evaluation board to the pc. additionally, analysis software provides easy ac- cess to the internal registers of the converters and provides a means to capture data and display the converters time domain, frequency domain, and noise histogram performance. 1.2 evaluation board overview the board is partitioned into two main sections: an- alog and digital. the analog section consists of the either the cs5521, cs5522, CS5523, cs5524 or cs5528, a precision voltage reference, and the cir- cuitry to generate a negative voltage. the digital section consists of the 80c51 microcontroller, the hardware test switches, the reset circuitry, and the rs-232 interface. the cs5521/22/23/24/28 is designed to digitize low level signals while operating from a 32.768 khz crystal. as shown in figures 1 and 2, a thermocouple can be connected to the converters inputs via j1s ain+ and ain- inputs. note, a sim- ple rc network filters the thermocouples output to reduce any interference picked up by the thermo- couple leads. the evaluation board provides two voltage refer- ence options, on-board and external. with hdr5s jumpers in positions 1 and 4, the lt1019 provides 2.5 volts (the lt1019 was chosen for its low drift, typically 5ppm/c). by setting hdr5s jumpers to position 2 and 3, the user can supply an external voltage reference to j2s ref+ and ref- inputs (application note 4 on the web details various voltage references). the a/d converters serial interfaces are spi tm and microwire tm compatible. the interface control lines (cs , sdi, sdo, and sclk) are con- nected to the 80c51 microcontroller via port one. to interface a different microcontroller to the adc chip, the control lines to the adc are available at hdr6 (header 6). however, to connect an external microcontroller to the header, the evaluation board must be modified in one of three ways: 1) cut the interface control traces going to the on-board 80c51 microcontroller, 2) remove resistors r1-r6, or 3) remove the 80c51 microcontroller from its socket on the evaluation board. figure 3 illustrates the schematic of the digital sec- tion. it contains the microcontroller, a motorola mc145407 interface chip, and test switches. the test switches aid in debugging communication problems between the cdb5521/22/23/24/28 and the pc. the microcontroller derives its clock from an 11.0592 mhz crystal. from this, the controller is configured to communicate via rs-232 at 9600 baud, no parity, 8-bit data, and 1 stop bit. cdb5521/22/23/24/28 ds317db2 5 1 c29 10 f c14 0.1f 2 +5v analog r15 10 w 14 c15 0.1f c30 10f 10 11 y2 32.768khz va+ agnd vd+ xin xout 9 cs 8 sdi 12 sdo 15 sclk 6 a0 16 a1 13 dgnd to figure 3 u6 cs5521 cs5522* c32 0.1f hdr1 c33 0.1f hdr2 c34 0.1f hdr8 c2 4700pf c3 4700pf r17 301 w r18 301 w r25 301 w 1 2 3 4 ain1+ ain1- ain2+ ain2- ain1+ ain1- ain2+ hdr5 3 4 18 20 19 vref+ vref- c16 0.1f r24 49.9 w u4 lt1019 r7 20k w gnd out in c20 0.1 f +5v analog trim c1 4700pf r21 301 w r22 301 w +5v analog ref+ ref- jp3 j2 jp4 jp5 jp6 c41 0.1 f c40 0.1f 5 nbv 337 gnd hdr4 d3 1n4148 7 cpd c9 0.033 f d2 1n4148 cpd c22 10 f d5 bat85 + u2 lm337_lz r23 1k w r16 1k w c11 0.1f + adj vout vin c21 1 f + -5v analog j1 jp7 ain2- 17 c35 0.1 f hdr9 r26 301 w * cs5521 and cs5522 are interchangeable figure 1. cs5522 analog section cdb5521/22/23/24/28 6 ds317db2 1 c29 10 f c14 0.1f 2 +5v analog r15 10 w 16 c15 0.1f c30 10f 12 13 y2 32.768khz va+ agnd vd+ xin xout 11 cs 10 sdi 14 sdo 17 sclk 8 a0 18 a1 15 dgnd to figure 3 7 nbv 337 gnd hdr4 d3 1n4148 9 cpd c9 0.033 f d2 1n4148 u3 CS5523 cs5524 cs5528* c32 0.1 f hdr1 c33 0.1f hdr2 c34 0.1f hdr8 c35 0.1f hdr9 c2 4700pf c3 4700pf r17 301 w r18 301 w r25 301 w r26 301 w ain1+/ain1 ain1-/ain2 ain2+/ain3 ain2-/ain4 3 4 22 21 cpd c22 10f d5 bat85 + u2 lm337_lz r23 1k w r16 1k w c11 0.1f + adj vout vin c21 1 f + -5v analog c36 0.1 f hdr11 c37 0.1f hdr12 c38 0.1f hdr13 c39 0.1f hdr14 c4 4700pf c31 4700pf r27 301 w r28 301 w r29 301 w r30 301 w ain3+ain5 ain3-/ain6 ain4+/ain7 ain4-/ain8 5 6 20 19 1 2 3 4 ain1+ ain1- ain2+ ain2- 5 6 7 8 ain3+ ain3- ain4+ ain4- hdr5 24 23 vref+ vref- c16 0.1f r24 49.9 w u4 lt1019 r7 20k w gnd out in c20 0.1 f +5v analog trim c1 4700pf r21 301 w r22 301 w +5v analog ref+ ref- jp3 j2 jp4 jp5 jp6 c41 0.1 f c40 0.1f j1 jp7 * * CS5523, cs5524 and cs5528 are interchangeable figure 2. cs5524/28 analog section cdb5521/22/23/24/28 ds317db2 7 cs r1 1 200 w sdi r2 2 200 w sdo r3 3 200 w sclk r4 4 200 w a0 r5 5 200 w a1 r6 6 200 w 18 y1 11.0592mhz 19 c23 33pf c0g c24 33pf c0g 9 +5v digital 40 +5v digital 39 r13 10k w + 1 8 + 2 7 + 3 6 + 4 5 r12 5.11k w r11 5.11k w r10 5.11k w 14 13 12 11 10 c7 47 f c17 0.1f + test switch 1 test switch 2 test switch 3 21 22 23 24 s1 d1 led_555_5003 reset comm gaincal offsetcal jp2 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 xtal1 xtal2 c19 0.1f bypass cap reset +5v digital r9 750k w c18 0.1f d4 1n4148 rst vss 20 vdd p0.0 p3.0 p3.1 p3.2 p3.3 p3.4 p2.0 p2.1 p2.2 p2.3 from rs-232 txd rxd tp71 tp72 16 15 14 13 12 11 normal loopback c28 10f + 24 u1 mc145407 c27 10f + 3 1 c25 10f + 18 20 5 6 7 8 9 10 c2- c2+ c1- c1+ vcc vdd 17 +5v digital c26 10f + r14 10k w 5 6 7 8 4 1 9 3 2 ri txd rxd rts cts dtr dsr dcd um1 80c51 from figure 1, 2 cs sdi a1 a0 sclk sdo hdr6 to rs-232 hdr7 19 figure 3. digital section cdb5521/22/23/24/28 8 ds317db2 1.3 using the evaluation board the cs5521/22/23/24/28 are highly integrated adcs. they contain a multiplexer, an instrumenta- tion amplifier (ia), a programmable gain amplifier (pga), an on-chip charge pump drive (cpd), and programmable output word rates (owr). the ia provides a set gain of 20 while the pga sets the in- put levels of the adc at either 25 mv, 55 mv, 100 mv, 1 v, 2.5 v, or 5 v (for vref = 2.5 v). the cpd provides a square wave output. this out- put, along with two diodes and two capacitors, is used to supply the negative supply to the ia, en- abling measurements of ground referenced signals. the adcs digital filter allows the user to select output word rates (owrs) from 1.88 hz up to 101 hz. higher output word rates can be attained when a faster clock source is used. since the cs5521/22/23/24/28 have such a high degree of in- tegration and flexibility, the cs5521/23 or cs5522/24/28 data sheet should be read thorough- ly before and consulted during the use of the cdb5521/22/23/24/28. table 1 lists the different headers on the cdb5521/22/23/24/28 and their functions. the locations of these headers are marked on the top of the board, and the silkscreen and layout of the board can also be found at the end of this document in figures 12, 13, and 14 for ref- erence. 1.4. power connections figure 4 illustrates the power supply connections to the evaluation board. the +5 v analog supplies the analog section of the evaluation board, the lt1019 and the adc. the -5 v analog supplies the nega- tive bias voltage circuitry. the +5 v digital sup- plies a separate five volts to the digital section of the evaluation board, the 80c51, the reset circuitry, and the rs-232 interface circuitry. 1.5 negative bias voltage the evaluation board provides three means of sup- plying the negative bias voltage (nbv). hdr4 (header 4) selects between them. when hrd4 is in position one, the lm337 supplies nbv with an ad- justable voltage. r16 is used to adjust this voltage between -1.25 v and -5 v. when in position two, hdr4 grounds nbv. and by setting hdr4 to po- sition three, the converters charge pump drive provides nbv with a dc rectified voltage, nominal- ly -2.1 v. note: nbv should not exceed a voltage more negative than -3.0 v. +5v analog -5v analog z3 p6ke6v8p + c8 47 f c13 0.1f z1 p6ke6v8p + c5 47f c10 0.1f +5v digital z2 p6ke6v8p + c6 47f c12 0.1f +5v analog -5v analog +5v digital agnd dgnd figure 4. power supplies cdb5521/22/23/24/28 ds317db2 9 1.6 software the evaluation board comes with software and an rs-232 cable to link the evaluation board to the pc. the executable software was developed with lab windows/cvi tm and meant to run under win- dows tm 3.1 or later. after installing the software, read the readme.txt file for last minute changes in the software. additionally, section 2., part ii: soft- ware further details how to install and use the soft- ware 1.7. writing your own interface software tables 2 through 5 list the rs-232 commands used to communicate between the pc and the microcon- troller. to develop additional code to communi- cate to the evaluation board via rs-232, the following applies: to write to an internal adc reg- ister, choose the appropriate write command byte (see table 2), and transmit it lsb first. then, transmit the three data bytes lowest order byte (bits 7-0) first with the lsb of each byte transmitted first. these three data bytes provide the 24-bits of information to be written to the desired register. to read from an internal register, choose the appro- priate read command byte and transmit it lsb first. then, the microcontroller automatically acquires the adcs register contents and returns the 24-bits of information. the returned data is transmitted lowest order byte first with the lsb of each byte transmit- ted first. name function description hdr1 used to switch ain1+ (ain1 on cs5528) between j1 and agnd. hdr2 used to switch ain1- (ain2 on cs5528) between j1 and agnd. hdr3 does not exist. hdr4 used to switch the power for nbv from the lm337, cpd, or agnd. hdr5 used to switch vref+ and vref- pins from external j2 header to the on board lt1019 reference. hdr6 used to connect an external micro- controller. hdr7 used in conjunction with the self test modes to test the uart/rs232 com- munication link between the micro- controller and a pc. hdr8 used to switch ain2 + (ain3 on cs5528) between j1 and agnd. hdr9 used to switch ain2- (ain4 on cs5528) between j1 and agnd. hdr10 does not exist. hdr11 used to switch ain3+ (ain5 on cs5528) between j1 and agnd. hdr12 used to switch ain3- (ain6 on cs5528) between j1 and agnd. hdr13 used to switch ain4+ (ain7 on cs5528) between j1 and agnd. hdr14 used to switch ain4- (ain8 on cs5528) between j1 and agnd. table 1. header descriptions cdb5521/22/23/24/28 10 ds317db2 register read command (hex) write command (hex) offset register physical channel 1 09 01 offset register physical channel 2 19 11 offset register physical channel 3 29 21 offset register physical channel 4 39 31 offset register physical channel 5 49 41 offset register physical channel 6 59 51 offset register physical channel 7 69 61 offset register physical channel 8 79 71 gain register physical channel 1 0a 02 gain register physical channel 2 1a 12 gain register physical channel 3 2a 22 gain register physical channel 4 3a 32 gain register physical channel 5 4a 42 gain register physical channel 6 5a 52 gain register physical channel 7 6a 62 gain register physical channel 8 7a 72 configuration register 0b 03 conversion data fifo 0c --- channel setup registers 0d 05 table 2. microcontroller read/write commands via rs-232 perform conversion conversion command (hex) normal conversion on setup 1 80 normal conversion on setup 2 88 normal conversion on setup 3 90 normal conversion on setup 4 98 normal conversion on setup 5 a0 normal conversion on setup 6 a8 normal conversion on setup 7 b0 normal conversion on setup 8 b8 normal conversion on setup 9 c0 normal conversion on setup 10 c8 normal conversion on setup 11 d0 normal conversion on setup 12 d8 normal conversion on setup 13 e0 normal conversion on setup 14 e8 normal conversion on setup 15 f0 normal conversion on setup 16 f8 table 3. microcontroller conversion commands via rs-232 cdb5521/22/23/24/28 ds317db2 11 self-offset calibration calibration command (hex) self-offset calibration on setup 1 81 self-offset calibration on setup 2 89 self-offset calibration on setup 3 91 self-offset calibration on setup 4 99 self-offset calibration on setup 5 a1 self-offset calibration on setup 6 a9 self-offset calibration on setup 7 b1 self-offset calibration on setup 8 b9 self-offset calibration on setup 9 c1 self-offset calibration on setup 10 c9 self-offset calibration on setup 11 d1 self-offset calibration on setup 12 d9 self-offset calibration on setup 13 e1 self-offset calibration on setup 14 e9 self-offset calibration on setup 15 f1 self-offset calibration on setup 16 f9 self gain calibration calibration command (hex) self-gain calibration on setup 1 82 self-gain calibration on setup 2 8a self-gain calibration on setup 3 92 self-gain calibration on setup 4 9a self-gain calibration on setup 5 a2 self-gain calibration on setup 6 aa self-gain calibration on setup 7 b2 self-gain calibration on setup 8 ba self-gain calibration on setup 9 c2 self-gain calibration on setup 10 ca self-gain calibration on setup 11 d2 self-gain calibration on setup 12 da self-gain calibration on setup 13 e2 self-gain calibration on setup 14 ea self-gain calibration on setup 15 f2 self-gain calibration on setup 16 fa table 4. microcontroller self calibration commands via rs-232 cdb5521/22/23/24/28 12 ds317db2 system-offset calibration calibration command (hex) system-offset calibration on setup 1 85 system-offset calibration on setup 2 8d system-offset calibration on setup 3 95 system-offset calibration on setup 4 9d system-offset calibration on setup 5 a5 system-offset calibration on setup 6 ad system-offset calibration on setup 7 b5 system-offset calibration on setup 8 bd system-offset calibration on setup 9 c5 system-offset calibration on setup 10 cd system-offset calibration on setup 11 d5 system-offset calibration on setup 12 dd system-offset calibration on setup 13 e5 system-offset calibration on setup 14 ed system-offset calibration on setup 15 f5 system-offset calibration on setup 16 fd system gain calibration calibration command (hex) system-gain calibration on setup 1 86 system-gain calibration on setup 2 8e system-gain calibration on setup 3 96 system-gain calibration on setup 4 9e system-gain calibration on setup 5 a6 system-gain calibration on setup 6 ae system-gain calibration on setup 7 b6 system-gain calibration on setup 8 be system-gain calibration on setup 9 c6 system-gain calibration on setup 10 ce system-gain calibration on setup 11 d6 system-gain calibration on setup 12 de system-gain calibration on setup 13 e6 system-gain calibration on setup 14 ee system-gain calibration on setup 15 f6 system-gain calibration on setup 16 fe miscellaneous commands command variable # of normal conversions 1f serial port initialization 3f reset converter 4f arbitrary read sdo ef arbitrary write sdi ff table 5. microcontroller system calibration commands via rs-232 cdb5521/22/23/24/28 ds317db2 13 2. part ii: software 2.1 installation procedure to install the software: 1) turn on the pc, running windows 95 tm or lat- er. 2) insert the installation diskette #1 into the pc. 3) select the run option from the start menu. 4) at the prompt, type: a:\setup.exe cdb5521/22/23/24/28 14 ds317db2 2.3 menu bars overview the menu bar controls the link between windows and allows the user to exit the program. it also al- lows the user to initialize the serial port and load presaved data conversions from a file. the six prin- cipal windows are the start-up, the setup window, the power spectrum window (also referred to as the fft window), the histogram window, the time domain window, and the calibrate window. specifically, the menu bar has the following control items: ?menu to select, click on option menu from the menu bar, or use associated hot keys. the items asso- ciated with menu are listed and described be- low. - start-up window (f1) - setup window (f2) - power spectrum window (f3) - histogram window (f4) - time domain window (f5) - calibrate window (f6) these six menu items allow the user to navigate between the windows. they are available at all times via the menu bar or hot keys. ? setup to select, click on option setup from the menu bar. the functions available under setup are: - com1 - when selected, com1 is initial- ized to 9600 baud, no parity, 8 data bits, and 1 stop bit. - com2 - when selected, com2 is initial- ized to 9600 baud, no parity, 8 data bits, and 1 stop bit. - load from disk - used to load and display previously saved data conversions from a file. the file must comply with the cdb- capture file save format. the format is: part number, throughput (or sample rate), number of conversions, maximum range, and the data conversions. the user is prompted to enter the path and file name of previously saved data. to prevent hardware conflicts, this option is deactivated while in the setup window. - testrs232 - this test mode tests the abili- ty of the pc to communicate to the evalua- tion board. it consists of two subtests: 1) test the link between the pc and the rs- 232 interface circuitry; and 2) test the rs-232 link between the pc and the microcontroller. - hdr7 distinguishes these two subtests. set hdr7 to normal to test the complete com- munication link. or set hdr7 to loop back to test the link between the rs-232 circuitry and the pc. then, set the test switches to 110 and reset the evaluation board. the leds should indicate a binary six signifying that the hardware is ready to initiate the test. to complete the test, the user must initialize the pc. first, use the setup menu to select a communications port and then select the testrs232 option. from there, user prompts navigate the user through the test. the pc indicates if the test passes or fails. once either test is complete, the leds toggle to indicate that the test mode is complete. ? part allows user to select a different converter. ?quit allows user to exit program. cdb5521/22/23/24/28 ds317db2 15 2.4 setup window overview the setup window (figure 6) allows the user to read and write to the internal register of the con- verter in either binary or hexadecimal, and acquire real-time conversions. it has quick access control icons that quickly reset the converter, reset the con- verters serial port, or self-calibrate the converters offset and gain. the following are controls and in- dicators associated with this window. ?acquire data this is a control icon. when pressed, the pc transmits the collect single conversion command to the microcontroller. the microcontroller in turn collects a conversion from the adc and re- turns it to the pc. the pc stores the conversion and collects additional conversions to form a set. from the sample set collected, the high, the low, peak-to-peak, average, and standard deviation, are computed (the size of the data set is set by the num to average input) and then the display icons are updated. this process continues until the stop button is pressed, or until another win- dow is selected. note: the quick access control icons are disabled once acquire is selected. this eliminates potential hardware conflicts. ? binary icons input icons array to set/clear the 24 individual bits in the configuration or channel-setup regis- ters. the respective registers bit is set/cleared as soon as the icon is clicked. ? channel selects the setup that will be accessed to per- form conversions when acquire data is activat- ed. ? register decode box text display box that displays the decoded meaning of each bit in the configuration regis- ter and the channel setup registers. use the pull- down menu above the register decode box to select between the different registers. ? hexadecimal icons nine input/display icons that allow a user to set/clear the 24 bits in the configuration, or channel setup registers via 6 hexadecimal nib- bles. if the upper nibbles in the registers are ze- ros, the leading zero nibbles need not be entered. ? num to average input icon that sets the size of the data conver- sion set referred to after the acquire icon is ac- tivated. ? reinitialize port this is a control icon. when pressed, 128 logic 1s followed by a logic 0 are sent to the adcs serial port to reset its port. it does not re- set the rs-232 link. ? reset a/d this is a control icon. when pressed, the micro- controller sends the appropriate commands to return the converter to its initial default state. ? stop stops the collection of conversion data. ? update icons this is a control icon. when pressed the config- uration and channel -setup registers contents are acquired. then, the configuration text box and the register content icons are updated. ? data fifo window this button opens the data fifo window when pressed. 2.5 data fifo window overview the following describes the controls available in the data fifo window (figure 7). cdb5521/22/23/24/28 16 ds317db2 ?acquire data this icon begins a conversion cycle based on the selection of mc, lp, and rc. depending on the status of these bits, the software will in- struct the converter to do single conversions or collect data in the fifo, and display the infor- mation on the screen. pressing the stop but- ton will end the conversion cycle. all other icons are disabled during the conversion cycles to avoid hardware conflicts. ? mc/lp/rc selection this box allows the user to select between the different types of conversion cycles available by modifying the mc, lp, and rc bits in the configuration register (refer to the cs5521/22/23/24/28 data sheet for more infor- mation). ? channel selects the setup that will be accessed for sin- gle conversions (mc = 0). for mc = 1, this box is ignored. ? data fifo boxes these boxes display the information returned from the data fifo buffer when mc = 1. for mc = 0, the single conversion will be displayed in box number 1. ? channel data boxes when using the cs5521/23, these boxes will contain the conversion channel information re- turned with the data word. when using the cs5522/24/28, these boxes will be inactive. 2.6 histogram window overview the following is a description of the controls and in- dicators associated with the histogram window (figure 11). many of the control icons are usable from the histogram window, the frequency do- main window, and the time domain window. for brevity, they are only described in this section. ? bin displays the x-axis value of the cursor on the histogram. ? cancel once selected, it allows a user to exit from the collect algorithm. if data conversion sam- ple sets larger than 64 are being collected and the cancel button is selected, it is recom- mended that the user reset the evaluation board. the board will eventually recover from the continuous collection mode, but the recovery time could be as long as 10 minutes. ? channel selects the setup that will be accessed to per- form conversions when collect is activat- ed. ? collect initiates the data conversion collection process. collect has two modes of operation: collect from file or collect from converter. to collect from a file an appropriate file from the setup- disk menu bar option must be selected. once a file is selected, its content is displayed in the graph. if the user is collecting real-time conver- sions to analyze, the appropriate com port must be selected. the user is then free to collect the preset number of conversions (preset by the config pop-up menu discussed below). no- tice, there is a significant acquisition time dif- ference between the two methods. ? config opens a pop-up panel to configure how much data is to be collected, and how to process the data once it is collected. the following are con- trols and indicators associated with the con- fig panel. - samples - user selection of 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, or 8192 con- versions. cdb5521/22/23/24/28 ds317db2 17 - window - used in the power spectrum window to calculate the fft. windowing algorithms include the blackman, black- man-harris, hand, 5-term hodie, and 7- term hodie. the 5-term hodie and 7-term hodie are windowing algorithms developed at crystal semiconductor. if information concerning these algorithms is needed, call technical support. - average - sets the number of consecutive ffts to perform and average. - limited noise bandwidth - limits the amount of noise in the converters band- width. when set to zero, no limited noise calculations are done. - fft bandwidth - used in the power spec- trum window to allow user-scalability of the frequency axis. when set to zero, the axis is auto-scaled to one-half the output word rate. - ok - accept the changes ? magnitude displays the y-axis value of the cursor on the histogram. ? maximum indicator for the maximum value of the collect- ed data set. ?mean indicator for the mean of the data sample set. ? minimum indicator for the minimum value of the collect- ed data set. ? output control that calls a pop-up menu. this menu controls three options: 1) save current data set to a file with the cdb- capture format 2) print current screen, or 3) print current graph. ? restore restores the display of the graph after zoom has been entered. ? std. dev. indicator for the standard deviation of the col- lected data set. ? variance indicates the variance for the current data set. ? zoom control icon that allows the operator to zoom in on a specific portion of the current graph. to zoom, click on the zoom icon, then click on the graph to select the first point (the 1st point is the top left corner of the zoom box). then click on the graph again to select the second point (the 2nd point is the bottom right corner of the zoom box). once an area has been zoomed in to, the output functions can be used to print a hard copy of that region. click on restore when done with the zoom function. 2.7 frequency domain window (i.e. fft) the following describe the controls and indicators associated with the frequency domain analysis (figure 8). ? cancel see description in section 2.6, histogram window overview . ? channel see description in section 2.6, histogram win- dow overview . ? collect see description in section 2.6, histogram win- dow overview . cdb5521/22/23/24/28 18 ds317db2 ? config see description in section 2.6, histogram win- dow overview . ? frequency displays the x-axis value of the cursor on the fft display. ? magnitude displays the y-axis value of the cursor on the fft display. ? output see description in section 2.6, histogram win- dow overview . ? s/d indicator for the signal-to-distortion ratio, 4 harmonics are used in the calculations (deci- bels). ? s/n+d indicator for the signal-to-noise + distortion ratio (decibels). ? snr indicator for the signal-to-noise ratio, first 4 harmonics are not included (decibels). ? s/pn indicator for the signal-to-peak noise ratio (decibels). ? zoom see description in section 2.6, histogram win- dow overview . ? # of avg displays the number of ffts averaged in the current display. 2.8 time domain window overview the following controls and indicators are associat- ed with the time domain analysis (figure 10). ? cancel see description in section 2.6, histogram win- dow overview . ? channel see description in section 2.6, histogram win- dow overview . ? collect see description in section 2.6, histogram win- dow overview . ? config see description in section 2.6, histogram win- dow overview . ? count displays current x-position of the cursor on the time domain display. ? magnitude displays current y-position of the cursor on the time domain display. ? maximum indicator for the maximum value of the collect- ed data set. ? minimum indicator for the minimum value of the collect- ed data set. ? output see description in section 2.6, histogram win- dow overview . ? zoom see description in section 2.6, histogram win- dow overview. cdb5521/22/23/24/28 ds317db2 19 2.9 calibration window overview the following controls and indicators are associat- ed with the calibration menu (figure 9). ? gain decode eight display boxes that displays the decoded meaning of each gain register. ? gain hexadecimal icons eight input/display icons that allow a user to set/clear the 24 bits in the eight gain registers via 6 hexadecimal nibbles. if the upper nibbles in the registers are zeros, then leading zero nibbles need to be entered. ? offset hexadecimal icons eight input/display icons that allow a user to set/clear the 24 bits in the eight offset registers via 6 hexadecimal nibbles. if the upper nibbles in the registers are zeros, then leading zero nibbles need to be entered. ? self-gain used to perform a self-gain calibration using the chosen setup. ? self-offset used to perform a self-offset calibration using the chosen setup. ? shift gain register sixteen input icons used to shift the contents on the gain registers either 1 bit left or right. once shifted the data at the respective gain registers ends is lost. ? system-gain used to perform a system-gain calibration us- ing the chosen setup. ? system-offset used to perform a system-offset calibration us- ing the chosen setup. ? update icons this is a control icon. when pressed the offset and gain registers are read. then, the register content icons are updated. 2.10 trouble shooting the evaluation board this section describes special test modes incorporated in the microcontroller software to diagnose hardware problems with the evaluation board. note: to enter these modes, set the test switches to the appropriate position and reset the evaluation board. to re-enter the normal operation mode, set the switches back to binary zero and reset the board again. ? test mode 0, normal mode this is the default mode of operation. to enter this mode, set the test switches to 000 and reset the board. the evaluation board allows normal read/writes to the adcs registers. all the leds toggle on then off after reset, and then only when communicating with the pc. ? test mode 1, loop back test this test mode checks the microcontrollers on- chip uart. to enter this mode, set test switch- es to 001, set hdr7 for loop back, and then re- set the board. if the communication works, all the led's toggle. otherwise, only 1/2 of the leds toggle to indicate a communication problem. ? test mode 2, read/write to adc this test mode tests the microcontrollers abil- ity to read and write to the adc. to enter this mode, set the switches to 010 and reset the board. in this test mode, the adcs configura- tion, offset, and gain registers are written to and then read from. if the correct data is read back, all the led's toggle. otherwise, only half of them toggle to indicate an error. cdb5521/22/23/24/28 20 ds317db2 ? test mode 3, continuously acquire single conversion this test mode repetitively acquires a single conversion. to enter this mode, set the test switches to 011 and press reset. a binary three is indicated on the leds. by probing hdr6 and using cs as a triggering pin, an oscillo- scope or logic analyzer will display in real-time how the microcontroller reads conversion data. ?test mode 4 reserved for future modifications. ? test mode 5, continuously read gain reg- ister this test mode repetitively acquires the gain registers default contents (0x800000 hex). to enter this mode, set the test switches to 101 and press reset. the leds should indicate a binary five. by probing hdr6 and using cs as a trig- gering pin, an oscilloscope or logic analyzer will display in real-time how the microcontrol- ler acquires a conversion. ? test mode 6, pc to microcontroller rs-232 communication link test this test mode tests the ability of the pc to communicate to the evaluation board. it con- sists of two subtests: 1) test the link between the pc and the rs-232 interface circuitry; and 2) test the rs-232 link between the pc and the microcontroller. hdr7 distinguishes these two subtests. set hdr7 to normal to test the complete commu- nication link. or set hdr7 to loop back to test the link between the rs-232 circuitry and the pc. then, set the test switches to 110 and reset the evaluation board. the leds should indi- cate a binary six signifying that the hardware is ready to initiate the test. to complete the test, the user must initialize the pc. first, use the setup menu to select a communications port and then select the testrs232 option. from there, user prompts navigate the user through the test. the pc indicates if the test passes or fails. once either test is complete, the leds toggle to indicate that the test mode is com- plete. ? test mode 7, toggle leds this test mode tests the evaluation board leds. to enter this mode, set the test switches to 111 and reset the board. if the mode passes, the leds toggle. note: remember, to return to the normal operating mode, set the test switches to binary zero, return hdr7 to normal, and reset the evaluation board. cdb5521/22/23/24/28 ds317db2 21 figure 5. main menu figure 6. setup window cdb5521/22/23/24/28 22 ds317db2 figure 7. data fifo window figure 8. frequency domain analysis cdb5521/22/23/24/28 ds317db2 23 figure 9. calibration menu figure 10. time domain analysis cdb5521/22/23/24/28 24 ds317db2 figure 11. histogram analysis (using the cs5524 with default register settings and 24-bit output words) cdb5521/22/23/24/28 ds317db2 25 figure 12. cdb5521/22/23/24/28 component side silkscreen cdb5521/22/23/24/28 26 ds317db2 figure 13. cdb5521/22/23/24/28 component side (top) cdb5521/22/23/24/28 ds317db2 27 figure 14. cdb5521/22/23/24/28 solder side (bottom) |
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